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authorDiana Picus <diana.picus@linaro.org>2018-01-30 07:54:58 +0000
committerDiana Picus <diana.picus@linaro.org>2018-01-30 07:54:58 +0000
commita2da03022ca3805226fa661b03830875c8aa0ce5 (patch)
tree7c08610a98d02dd9f66edf39728fc77f845ca6cb /llvm/lib/Target/ARM
parent4ed0ee7b5f6e209cd39506980869620eabff7aad (diff)
downloadbcm5719-llvm-a2da03022ca3805226fa661b03830875c8aa0ce5.tar.gz
bcm5719-llvm-a2da03022ca3805226fa661b03830875c8aa0ce5.zip
[ARM GlobalISel] Map G_FPTOSI and G_FPTOUI
Straightforward mapping (integer operand goes to GPR, floating point operand goes to FPR). llvm-svn: 323727
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp14
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 0e6073a5c80..2f9c53f82d4 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -303,6 +303,20 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
&ARM::ValueMappings[ARM::DPR3OpsIdx]});
break;
}
+ case G_FPTOSI:
+ case G_FPTOUI: {
+ LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
+ LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
+ if ((FromTy.getSizeInBits() == 32 || FromTy.getSizeInBits() == 64) &&
+ ToTy.getSizeInBits() == 32)
+ OperandsMapping =
+ FromTy.getSizeInBits() == 64
+ ? getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::DPR3OpsIdx]})
+ : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx],
+ &ARM::ValueMappings[ARM::SPR3OpsIdx]});
+ break;
+ }
case G_CONSTANT:
case G_FRAME_INDEX:
case G_GLOBAL_VALUE:
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