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authorAndrew Trick <atrick@apple.com>2013-01-09 03:36:49 +0000
committerAndrew Trick <atrick@apple.com>2013-01-09 03:36:49 +0000
commit9f0b95f260d05ab149cb790bc9e5ef16f8777a69 (patch)
tree56d12f398126280974627f45d51934ee6233abe3 /llvm/lib/Target/ARM
parent196bbc25711745032ab3d73ab946162dee7ba7cb (diff)
downloadbcm5719-llvm-9f0b95f260d05ab149cb790bc9e5ef16f8777a69.tar.gz
bcm5719-llvm-9f0b95f260d05ab149cb790bc9e5ef16f8777a69.zip
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. llvm-svn: 171946
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMScheduleA9.td3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleA9.td b/llvm/lib/Target/ARM/ARMScheduleA9.td
index 404634fee98..4191931a5ad 100644
--- a/llvm/lib/Target/ARM/ARMScheduleA9.td
+++ b/llvm/lib/Target/ARM/ARMScheduleA9.td
@@ -1887,6 +1887,9 @@ def CortexA9Model : SchedMachineModel {
let LoadLatency = 2; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
+ let ILPWindow = 10; // Don't reschedule small blocks to hide
+ // latency. Minimum latency requirements are already
+ // modeled strictly by reserving resources.
let MispredictPenalty = 8; // Based on estimate of pipeline depth.
let Itineraries = CortexA9Itineraries;
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