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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:04 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2017-02-11 01:53:04 +0000 |
| commit | 8425f453ef77e3e1e14f804195802eae80261bef (patch) | |
| tree | 11e00ea3e045a8088d2541cecd66d6ee05f45cec /llvm/lib/Target/ARM | |
| parent | fc979dc9ddf6a29977381a606846c762457d41de (diff) | |
| download | bcm5719-llvm-8425f453ef77e3e1e14f804195802eae80261bef.tar.gz bcm5719-llvm-8425f453ef77e3e1e14f804195802eae80261bef.zip | |
[ARM] Make f16 interleaved accesses expensive.
There are no vldN/vstN f16 variants, even with +fullfp16.
We could use the i16 variants, but, in practice, even with +fullfp16,
the f16 sequence leading to the i16 shuffle usually gets scalarized.
We'd need to improve our support for f16 codegen before getting there.
Teach the cost model to consider f16 interleaved operations as
expensive. Otherwise, we are all but guaranteed to end up with
a large block of scalarized vector code.
llvm-svn: 294819
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index 2b6b36bc3e6..90e4f3a7cc6 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -533,7 +533,8 @@ int ARMTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy); // vldN/vstN only support legal vector types of size 64 or 128 in bits. - if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128)) + if (NumElts % Factor == 0 && (SubVecSize == 64 || SubVecSize == 128) && + !VecTy->getScalarType()->isHalfTy()) return Factor; } |
