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| author | Sam Parker <sam.parker@arm.com> | 2017-09-18 14:28:51 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2017-09-18 14:28:51 +0000 |
| commit | 71efbe4c683577c335eee898c0a47e5d8ba0c386 (patch) | |
| tree | 30afb6bc84fad186881f8c35b5e92be408f45d2a /llvm/lib/Target/ARM | |
| parent | 00161c996106ff151227b8fc63e08597d58a3e7d (diff) | |
| download | bcm5719-llvm-71efbe4c683577c335eee898c0a47e5d8ba0c386.tar.gz bcm5719-llvm-71efbe4c683577c335eee898c0a47e5d8ba0c386.zip | |
[ARM] Implement isTruncateFree
Implement the isTruncateFree hooks, lifted from AArch64, that are
used by TargetTransformInfo. This allows simplifycfg to reduce the
test case into a single basic block.
Differential Revision: https://reviews.llvm.org/D37516
llvm-svn: 313533
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 20 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.h | 3 |
2 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e947ddc7031..02fbb1e811d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -12179,6 +12179,26 @@ EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size, return MVT::Other; } +// 64-bit integers are split into their high and low parts and held in two +// different registers, so the trunc is free since the low register can just +// be used. +bool ARMTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const { + if (!SrcTy->isIntegerTy() || !DstTy->isIntegerTy()) + return false; + unsigned NumBits1 = SrcTy->getPrimitiveSizeInBits(); + unsigned NumBits2 = DstTy->getPrimitiveSizeInBits(); + return NumBits1 > NumBits2; +} + +bool ARMTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const { + if (SrcVT.isVector() || DstVT.isVector() || !SrcVT.isInteger() || + !DstVT.isInteger()) + return false; + unsigned NumBits1 = SrcVT.getSizeInBits(); + unsigned NumBits2 = DstVT.getSizeInBits(); + return NumBits1 > NumBits2; +} + bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { if (Val.getOpcode() != ISD::LOAD) return false; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 40cf54586af..4836569919a 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -308,7 +308,8 @@ class InstrItineraryData; bool MemcpyStrSrc, MachineFunction &MF) const override; - using TargetLowering::isZExtFree; + bool isTruncateFree(Type *SrcTy, Type *DstTy) const override; + bool isTruncateFree(EVT SrcVT, EVT DstVT) const override; bool isZExtFree(SDValue Val, EVT VT2) const override; bool isVectorLoadExtDesirable(SDValue ExtVal) const override; |

