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| author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-09-30 15:56:34 +0000 |
|---|---|---|
| committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-09-30 15:56:34 +0000 |
| commit | 66eb921a822934585264598a3002587217d94d9f (patch) | |
| tree | 31d79bc6a81dc15bc7a6e487f01131509d028ba1 /llvm/lib/Target/ARM | |
| parent | f00472908a224653d67f268d9fb0c9d39d79e5dc (diff) | |
| download | bcm5719-llvm-66eb921a822934585264598a3002587217d94d9f.tar.gz bcm5719-llvm-66eb921a822934585264598a3002587217d94d9f.zip | |
Swift model: Fix uop description on some writes
Those writes really need two/three uops.
llvm-svn: 191677
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleSwift.td | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMScheduleSwift.td b/llvm/lib/Target/ARM/ARMScheduleSwift.td index 2a41616b409..8d7dbc24609 100644 --- a/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -1345,20 +1345,25 @@ let SchedModel = SwiftModel in { // 4.2.20 Integer Load Signextended def SwiftWriteP2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 3; + let NumMicroOps = 2; } def SwiftWriteP2P01FourCyle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 4; + let NumMicroOps = 2; } def SwiftWriteP2P01P01FourCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01, SwiftUnitP01]> { let Latency = 4; + let NumMicroOps = 3; } def SwiftWriteP2P2ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2]> { let Latency = 3; + let NumMicroOps = 2; } def SwiftWriteP2P2P01ThreeCycle : SchedWriteRes<[SwiftUnitP2, SwiftUnitP2, - SwiftUnitP01]> { + SwiftUnitP01]> { let Latency = 3; + let NumMicroOps = 3; } def SwiftWrBackOne : SchedWriteRes<[]> { let Latency = 1; @@ -1399,7 +1404,10 @@ let SchedModel = SwiftModel in { def SwiftWriteLM#Lat#Cy : SchedWriteRes<[SwiftUnitP2]> { let Latency = Lat; } - def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { let Latency = Lat; } + def SwiftWriteLM#Lat#CyNo : SchedWriteRes<[]> { + let Latency = Lat; + let NumMicroOps = 0; + } } // Predicate. foreach NumAddr = 1-16 in { @@ -1520,6 +1528,7 @@ let SchedModel = SwiftModel in { // 4.2.25 Integer Store, Multiple def SwiftWriteStIncAddr : SchedWriteRes<[SwiftUnitP2, SwiftUnitP01]> { let Latency = 0; + let NumMicroOps = 2; } foreach NumAddr = 1-16 in { def SwiftWriteSTM#NumAddr : WriteSequence<[SwiftWriteStIncAddr], NumAddr>; |

