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authorSjoerd Meijer <sjoerd.meijer@arm.com>2019-05-30 08:07:06 +0000
committerSjoerd Meijer <sjoerd.meijer@arm.com>2019-05-30 08:07:06 +0000
commit5857bf5d1e5a5ffe5ae51a38514ee55495c0cc69 (patch)
tree972015e6023e006e209274415c36d602d9267d75 /llvm/lib/Target/ARM
parent9b8a0d7110e97db67f48368ee623d06cbb6075a5 (diff)
downloadbcm5719-llvm-5857bf5d1e5a5ffe5ae51a38514ee55495c0cc69.tar.gz
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[ARM] Add an MVE execution domain
MVE architecturally specifies a 'beat' system in which a vector instruction executed now will complete its actual operation over the next four cycles, so it can overlap with the execution of the previous and next MVE instruction. This makes it generally an advantage to avoid moving values back and forth between MVE registers and anywhere else, if there's any sensible way to do the same processing in whatever register type the values already occupied. That's just what the 'execution domain' system is supposed to achieve. So here we add a new execution domain which will contain all the MVE vector instructions when they are added. Patch by: Simon Tatham Differential Revision: https://reviews.llvm.org/D60703 llvm-svn: 362068
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrFormats.td9
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h5
2 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td
index 00a72026c27..b09aa8a97df 100644
--- a/llvm/lib/Target/ARM/ARMInstrFormats.td
+++ b/llvm/lib/Target/ARM/ARMInstrFormats.td
@@ -120,14 +120,15 @@ def IndexModePost : IndexMode<2>;
def IndexModeUpd : IndexMode<3>;
// Instruction execution domain.
-class Domain<bits<3> val> {
- bits<3> Value = val;
+class Domain<bits<4> val> {
+ bits<4> Value = val;
}
def GenericDomain : Domain<0>;
def VFPDomain : Domain<1>; // Instructions in VFP domain only
def NeonDomain : Domain<2>; // Instructions in Neon domain only
def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
+def MVEDomain : Domain<8>; // Instructions in MVE and ARMv8.1m
//===----------------------------------------------------------------------===//
// ARM special operands.
@@ -324,8 +325,8 @@ class InstTemplate<AddrMode am, int sz, IndexMode im,
let TSFlags{12-7} = Form;
let TSFlags{13} = isUnaryDataProc;
let TSFlags{14} = canXformTo16Bit;
- let TSFlags{17-15} = D.Value;
- let TSFlags{18} = thumbArithFlagSetting;
+ let TSFlags{18-15} = D.Value;
+ let TSFlags{19} = thumbArithFlagSetting;
let Constraints = cstr;
let Itinerary = itin;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
index 21a7f2dfb33..a654e645ba0 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h
@@ -385,16 +385,17 @@ namespace ARMII {
// instruction. Used by the parser to determine whether to require the 'S'
// suffix on the mnemonic (when not in an IT block) or preclude it (when
// in an IT block).
- ThumbArithFlagSetting = 1 << 18,
+ ThumbArithFlagSetting = 1 << 19,
//===------------------------------------------------------------------===//
// Code domain.
DomainShift = 15,
- DomainMask = 7 << DomainShift,
+ DomainMask = 15 << DomainShift,
DomainGeneral = 0 << DomainShift,
DomainVFP = 1 << DomainShift,
DomainNEON = 2 << DomainShift,
DomainNEONA8 = 4 << DomainShift,
+ DomainMVE = 8 << DomainShift,
//===------------------------------------------------------------------===//
// Field shifts - such shifts are used to set field while generating
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