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| author | JF Bastien <jfb@google.com> | 2013-07-12 23:33:03 +0000 |
|---|---|---|
| committer | JF Bastien <jfb@google.com> | 2013-07-12 23:33:03 +0000 |
| commit | 583db650318268d34ddf9b2ae69977fa038cff56 (patch) | |
| tree | 1df77ecd7bf5ad31699046eb6ae8e6015ebd7ac4 /llvm/lib/Target/ARM | |
| parent | 44ccf3ebd2dcdb30bf82fcdf902dd714e0e4f1cb (diff) | |
| download | bcm5719-llvm-583db650318268d34ddf9b2ae69977fa038cff56.tar.gz bcm5719-llvm-583db650318268d34ddf9b2ae69977fa038cff56.zip | |
Fix ARM paired GPR COPY lowering
ARM paired GPR COPY was being lowered to two MOVr without CC. This
patch puts the CC back.
My test is a reduction of the case where I encountered the issue,
64-bit atomics use paired GPRs.
The issue only occurs with selectionDAG, FastISel doesn't encounter it
so I didn't bother calling it.
llvm-svn: 186226
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 5283d7b3623..d6701782a47 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -745,6 +745,9 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (Opc == ARM::VORRq) Mov.addReg(Src); Mov = AddDefaultPred(Mov); + // MOVr can set CC. + if (Opc == ARM::MOVr) + Mov = AddDefaultCC(Mov); } // Add implicit super-register defs and kills to the last instruction. Mov->addRegisterDefined(DestReg, TRI); |
