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authorRafael Espindola <rafael.espindola@gmail.com>2013-12-02 04:55:42 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2013-12-02 04:55:42 +0000
commit50712a456d63dcf57d369f9c0b7e71f3cdca3590 (patch)
treea31267b7b2ac0cae3493fe4d8ce9758a80327ebc /llvm/lib/Target/ARM
parent43d937fc3e3fafe595da55e396e124ab0eda88b7 (diff)
downloadbcm5719-llvm-50712a456d63dcf57d369f9c0b7e71f3cdca3590.tar.gz
bcm5719-llvm-50712a456d63dcf57d369f9c0b7e71f3cdca3590.zip
Change the default of AsmWriterClassName and isMCAsmWriter.
llvm-svn: 196065
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARM.td13
1 files changed, 0 insertions, 13 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index ed827c47ceb..ca2ddfdff3b 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -391,17 +391,6 @@ include "ARMInstrInfo.td"
def ARMInstrInfo : InstrInfo;
-
-//===----------------------------------------------------------------------===//
-// Assembly printer
-//===----------------------------------------------------------------------===//
-// ARM Uses the MC printer for asm output, so make sure the TableGen
-// AsmWriter bits get associated with the correct class.
-def ARMAsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
@@ -409,6 +398,4 @@ def ARMAsmWriter : AsmWriter {
def ARM : Target {
// Pull in Instruction Info:
let InstructionSet = ARMInstrInfo;
-
- let AssemblyWriters = [ARMAsmWriter];
}
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