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| author | Peter Collingbourne <peter@pcc.me.uk> | 2018-10-24 18:10:38 +0000 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2018-10-24 18:10:38 +0000 |
| commit | 4bb928c11010e1ba38b19ee89ac77ed1d096a76a (patch) | |
| tree | badb64132e1de3362c5f016c624786f5c325cca2 /llvm/lib/Target/ARM | |
| parent | f124275cf9ddc8b8da68349f5f166640b31473be (diff) | |
| download | bcm5719-llvm-4bb928c11010e1ba38b19ee89ac77ed1d096a76a.tar.gz bcm5719-llvm-4bb928c11010e1ba38b19ee89ac77ed1d096a76a.zip | |
ARM: Use BKPT instead of TRAP to implement llvm.debugtrap.
The BKPT instruction is specified to cause a software breakpoint,
and at least on Linux results in a SIGTRAP. This makes it more
suitable for implementing debugtrap than TRAP (aka UDF #254), which
is specified to cause an undefined instruction exception and results
in a SIGILL on Linux.
Moreover, BKPT is not marked as a terminator, which is not only
consistent with the IR instruction but allows the analyzeBlock
function to correctly analyze a basic block containing the instruction,
which fixes an assertion failure in the machine block placement pass
previously triggered by the included test case.
Because BKPT is only supported starting with ARMv5T, we continue to
use UDF #254 when targeting v4T.
Differential Revision: https://reviews.llvm.org/D53614
llvm-svn: 345171
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 3 |
3 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 2f4bc46f932..8c18477005f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -956,6 +956,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BlockAddress, MVT::i32, Custom); setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal); // Use the default implementation. setOperationAction(ISD::VASTART, MVT::Other, Custom); diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index fc8ed95ce8b..76f8414e8f0 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -221,6 +221,7 @@ def HasV4T : Predicate<"Subtarget->hasV4TOps()">, def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">, AssemblerPredicate<"HasV5TOps", "armv5t">; +def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate<"HasV5TEOps", "armv5te">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">, @@ -2200,6 +2201,9 @@ def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary, let Inst = 0xe7ffdefe; } +def : Pat<(debugtrap), (BKPT 0)>, Requires<[IsARM, HasV5T]>; +def : Pat<(debugtrap), (UDF 254)>, Requires<[IsARM, NoV5T]>; + // Address computation and loads and stores in PIC mode. let isNotDuplicable = 1 in { def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p), diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 88aab47a79b..8b85db7e685 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -1380,6 +1380,9 @@ def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8", let Inst{7-0} = imm8; } +def : Pat<(debugtrap), (tBKPT 0)>, Requires<[IsThumb, HasV5T]>; +def : Pat<(debugtrap), (tUDF 254)>, Requires<[IsThumb, NoV5T]>; + def t__brkdiv0 : TI<(outs), (ins), IIC_Br, "__brkdiv0", [(int_arm_undefined 249)]>, Encoding16, Requires<[IsThumb, IsWindows]> { |
