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| author | Owen Anderson <resistor@mac.com> | 2010-12-09 20:27:52 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2010-12-09 20:27:52 +0000 |
| commit | 3ef19d9d48ea21def23eb4c012ae9f8c17c00432 (patch) | |
| tree | 12d06d4fd4f8b0e20e23375e610f5546c73fd491 /llvm/lib/Target/ARM | |
| parent | 68b27eb9d11061b2ca3ef757b4952c26f0ca072b (diff) | |
| download | bcm5719-llvm-3ef19d9d48ea21def23eb4c012ae9f8c17c00432.tar.gz bcm5719-llvm-3ef19d9d48ea21def23eb4c012ae9f8c17c00432.zip | |
Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating
the offset. Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this. It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.
llvm-svn: 121408
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMAsmBackend.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/ARMAsmBackend.cpp index 6be9f9288e2..606437efbb4 100644 --- a/llvm/lib/Target/ARM/ARMAsmBackend.cpp +++ b/llvm/lib/Target/ARM/ARMAsmBackend.cpp @@ -100,10 +100,10 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { } case ARM::fixup_arm_ldst_pcrel_12: // ARM PC-relative values are offset by 8. - Value -= 6; + Value -= 4; case ARM::fixup_t2_ldst_pcrel_12: { // Offset by 4, adjusted by two due to the half-word ordering of thumb. - Value -= 2; + Value -= 4; bool isAdd = true; if ((int64_t)Value < 0) { Value = -Value; diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index c81833b28f8..4d8791c9989 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -47,7 +47,8 @@ public: const static MCFixupKindInfo Infos[] = { // name off bits flags { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | + MCFixupKindInfo::FKF_IsAligned}, { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, |
