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| author | Sam Parker <sam.parker@arm.com> | 2019-03-14 10:57:40 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2019-03-14 10:57:40 +0000 |
| commit | 3b2ba20afd4c4866aae5efc95739cc876fc2cb11 (patch) | |
| tree | 7c6d9a898eff915c149303f5ef6f58a6feec08ec /llvm/lib/Target/ARM | |
| parent | c03a95d46576a5de3b3c15fc5d818cf0fe66668f (diff) | |
| download | bcm5719-llvm-3b2ba20afd4c4866aae5efc95739cc876fc2cb11.tar.gz bcm5719-llvm-3b2ba20afd4c4866aae5efc95739cc876fc2cb11.zip | |
[ARM] Run ARMParallelDSP in the IRPasses phase
Run EarlyCSE before ParallelDSP and do this in the backend IR opt
phase.
Differential Revision: https://reviews.llvm.org/D59257
llvm-svn: 356130
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetMachine.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 401843c1e0f..bd075cda2e4 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -403,6 +403,12 @@ void ARMPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); + // Run the parallel DSP pass and its helpers. + if (getOptLevel() == CodeGenOpt::Aggressive) { + addPass(createEarlyCSEPass()); + addPass(createARMParallelDSPPass()); + } + // Match interleaved memory accesses to ldN/stN intrinsics. if (TM->getOptLevel() != CodeGenOpt::None) addPass(createInterleavedAccessPass()); @@ -415,9 +421,6 @@ void ARMPassConfig::addCodeGenPrepare() { } bool ARMPassConfig::addPreISel() { - if (getOptLevel() != CodeGenOpt::None) - addPass(createARMParallelDSPPass()); - if ((TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge == cl::BOU_UNSET) || EnableGlobalMerge == cl::BOU_TRUE) { |
