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| author | Chad Rosier <mcrosier@apple.com> | 2012-11-27 21:46:46 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@apple.com> | 2012-11-27 21:46:46 +0000 |
| commit | 2ec7db0968e1f6cef491a37d7f7be142f62c57fc (patch) | |
| tree | 3d8214f34d28df05ec9fefaed6d97f158ef589bf /llvm/lib/Target/ARM | |
| parent | 2bbf09e39eef15b0a724de78217d6013713c5029 (diff) | |
| download | bcm5719-llvm-2ec7db0968e1f6cef491a37d7f7be142f62c57fc.tar.gz bcm5719-llvm-2ec7db0968e1f6cef491a37d7f7be142f62c57fc.zip | |
[arm fast-isel] Appease the machine verifier by using the proper register
classes. Also a bit of cleanup.
rdar://12719844
llvm-svn: 168728
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMFastISel.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMFastISel.cpp b/llvm/lib/Target/ARM/ARMFastISel.cpp index 5de555614cc..96e2ce9f38d 100644 --- a/llvm/lib/Target/ARM/ARMFastISel.cpp +++ b/llvm/lib/Target/ARM/ARMFastISel.cpp @@ -1667,7 +1667,6 @@ bool ARMFastISel::SelectSelect(const Instruction *I) { // Things need to be register sized for register moves. if (VT != MVT::i32) return false; - const TargetRegisterClass *RC = TLI.getRegClassFor(VT); unsigned CondReg = getRegForValue(I->getOperand(0)); if (CondReg == 0) return false; @@ -1700,14 +1699,16 @@ bool ARMFastISel::SelectSelect(const Instruction *I) { .addReg(CondReg).addImm(0)); unsigned MovCCOpc; + const TargetRegisterClass *RC; if (!UseImm) { + RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; } else { - if (!isNegativeImm) { + RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; + if (!isNegativeImm) MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; - } else { + else MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; - } } unsigned ResultReg = createResultReg(RC); if (!UseImm) @@ -2589,7 +2590,7 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH; } else { Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; - RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass; + RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; } break; case MVT::i8: |
