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authorScott Douglass <sdouglass@arm.com>2015-07-09 14:13:48 +0000
committerScott Douglass <sdouglass@arm.com>2015-07-09 14:13:48 +0000
commit2740a6372514329605d0d43ddbb4a8399d48ed29 (patch)
tree31f8007a7e8fb406274fd30d9b159c5acacaea43 /llvm/lib/Target/ARM
parent47a3fce4611df71732252c783392e15c3e9d05a0 (diff)
downloadbcm5719-llvm-2740a6372514329605d0d43ddbb4a8399d48ed29.tar.gz
bcm5719-llvm-2740a6372514329605d0d43ddbb4a8399d48ed29.zip
[ARM] Don't be overzealous converting Thumb1 3 to 2 operands
Differential Revision: http://reviews.llvm.org/D11056 llvm-svn: 241801
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index cea7070abd0..0ae6925c28b 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -5512,6 +5512,11 @@ void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
Op5.isReg())
Transform = false;
+
+ // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
+ // 3-bits because the ARMARM says not to.
+ if ((Mnemonic == "add" || Mnemonic == "sub") && Op5.isImm0_7())
+ Transform = false;
}
if (Transform)
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