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authorJim Grosbach <grosbach@apple.com>2010-09-16 17:43:25 +0000
committerJim Grosbach <grosbach@apple.com>2010-09-16 17:43:25 +0000
commit218e22da8b252de24ddafbdeedeaf50ab7527b87 (patch)
treec9c39dadb627c989f4982212a0d2df0ee2db3c89 /llvm/lib/Target/ARM
parent94532cb297f9ddbef0390b3047e6b9cbec592382 (diff)
downloadbcm5719-llvm-218e22da8b252de24ddafbdeedeaf50ab7527b87.tar.gz
bcm5719-llvm-218e22da8b252de24ddafbdeedeaf50ab7527b87.zip
MC-ization of the PICLDR pseudo. Next up, adding the other variants
(PICLDRB, et. al.) and PICSTR* llvm-svn: 114098
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMAsmPrinter.cpp29
-rw-r--r--llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp5
2 files changed, 33 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index cea9fd5aaec..df75ff203dc 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1351,6 +1351,35 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
OutStreamer.EmitInstruction(AddInst);
return;
}
+ case ARM::PICLDR: {
+ // This is a pseudo op for a label + instruction sequence, which looks like:
+ // LPC0:
+ // ldr r0, [pc, r0]
+ // The LCP0 label is referenced by a constant pool entry in order to get
+ // a PC-relative address at the ldr instruction.
+
+ // Emit the label.
+ // FIXME: MOVE TO SHARED PLACE.
+ unsigned Id = (unsigned)MI->getOperand(2).getImm();
+ const char *Prefix = MAI->getPrivateGlobalPrefix();
+ MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
+ + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
+ OutStreamer.EmitLabel(Label);
+
+ // Form and emit the load
+ MCInst LdrInst;
+ LdrInst.setOpcode(ARM::LDR);
+ LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ LdrInst.addOperand(MCOperand::CreateReg(ARM::PC));
+ LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
+ LdrInst.addOperand(MCOperand::CreateImm(0));
+ // Add predicate operands.
+ LdrInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
+ LdrInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
+ OutStreamer.EmitInstruction(LdrInst);
+
+ return;
+ }
case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
/// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
/// in the function. The first operand is the ID# for this instruction, the
diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
index 37c4f75e822..2e48905791c 100644
--- a/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
+++ b/llvm/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
@@ -384,7 +384,10 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O,
const char *Modifier) {
- assert(0 && "FIXME: Implement printAddrModePCOperand");
+ // All instructions using addrmodepc are pseudos and should have been
+ // handled explicitly in printInstructionThroughMCStreamer(). If one got
+ // here, it wasn't, so something's wrong.
+ assert(0 && "Unhandled addrmodepc operand!");
}
void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
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