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| author | Chris Lattner <sabre@nondot.org> | 2008-01-17 19:59:44 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-17 19:59:44 +0000 |
| commit | 1ea55cf8166d46b1518b83dce5c14f1e175ac03c (patch) | |
| tree | 46a8c6da33bec80d1103e03cebcd48438c1acd71 /llvm/lib/Target/ARM | |
| parent | 9f7fed1c1bd315e291a49dbe815baf3bd7d1c0a0 (diff) | |
| download | bcm5719-llvm-1ea55cf8166d46b1518b83dce5c14f1e175ac03c.tar.gz bcm5719-llvm-1ea55cf8166d46b1518b83dce5c14f1e175ac03c.zip | |
This commit changes:
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 4 |
3 files changed, 2 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 4d8a2372d01..bdaf6b2fc50 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -125,6 +125,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { addRegisterClass(MVT::f32, ARM::SPRRegisterClass); addRegisterClass(MVT::f64, ARM::DPRRegisterClass); + + setTruncStoreAction(MVT::f64, MVT::f32, Expand); } computeRegisterProperties(); diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 1027b6c3d45..d3bce5d955b 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1404,14 +1404,6 @@ def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>; def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>; def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>; -// truncstore i1 -> truncstore i8 -def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst), - (STRB GPR:$src, addrmode2:$dst)>; -def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), - (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>; -def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset), - (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>; - // smul* and smla* def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)), (SMULBB GPR:$a, GPR:$b)>; diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index d6fa76c9779..7880c235fcc 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -588,10 +588,6 @@ def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>; -// truncstore i1 -> truncstore i8 -def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst), - (tSTRB GPR:$src, t_addrmode_s1:$dst)>; - // Large immediate handling. // Two piece imms. |
