Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.

Summary:
This is the first patch in the series to migrate Triple's (which are ambiguous)
to TargetTuple's (which aren't).

For the moment, TargetTuple simply passes all requests to the Triple object it
holds. Once it has replaced Triple, it will start to implement the interface in
a more suitable way.

This change makes some changes to the public C++ API. In particular,
InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer()
now take TargetTuples instead of Triples. The other public C++ API's have
been left as-is for the moment to reduce patch size.

This commit also contains a trivial patch to clang to account for the C++ API
change.

Reviewers: rengolin

Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10969

llvm-svn: 247683

13 files changed, 86 insertions, 80 deletions

diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index f5f12472437..3a8556e4af7 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -558,7 +558,7 @@ void ARMAsmPrinter::emitAttributes() {
   const Triple &TT = TM.getTargetTriple();
   StringRef CPU = TM.getTargetCPU();
   StringRef FS = TM.getTargetFeatureString();
-  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
+  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TargetTuple(TT), CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 50e9e6a7397..0f2069474be 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -81,7 +81,7 @@ ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
-    : ARMGenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
+    : ARMGenSubtargetInfo(TargetTuple(TT), CPU, FS), ARMProcFamily(Others),
       ARMProcClass(None), stackAlignment(4), CPUString(CPU), IsLittle(IsLittle),
       TargetTriple(TT), Options(TM.Options), TM(TM),
       FrameLowering(initializeFrameLowering(CPU, FS)),
@@ -159,7 +159,8 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Insert the architecture feature derived from the target triple into the
   // feature string. This is important for setting features that are implied
   // based on the architecture version.
-  std::string ArchFS = ARM_MC::ParseARMTriple(TargetTriple, CPUString);
+  std::string ArchFS =
+      ARM_MC::ParseARMTargetTuple(TargetTuple(TargetTriple), CPUString);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 1fe2dbe7866..ada3aa7d2a3 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -779,45 +779,49 @@ static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
 
 MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
                                         const MCRegisterInfo &MRI,
-                                        const Triple &TheTriple, StringRef CPU,
+                                        const TargetTuple &TT, StringRef CPU,
                                         bool isLittle) {
-  switch (TheTriple.getObjectFormat()) {
+  switch (TT.getObjectFormat()) {
   default:
     llvm_unreachable("unsupported object format");
-  case Triple::MachO: {
-    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
-    return new ARMAsmBackendDarwin(T, TheTriple, CS);
-  }
-  case Triple::COFF:
-    assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
-    return new ARMAsmBackendWinCOFF(T, TheTriple);
-  case Triple::ELF:
-    assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
-    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
-    return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
+  case TargetTuple::MachO: {
+    MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TT.getArchName());
+    return new ARMAsmBackendDarwin(T, TT, CS);
+  }
+  case TargetTuple::COFF:
+    assert(TT.isOSWindows() && "non-Windows ARM COFF is not supported");
+    return new ARMAsmBackendWinCOFF(T, TT);
+  case TargetTuple::ELF:
+    assert(TT.isOSBinFormatELF() && "using ELF for non-ELF target");
+    uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
+    return new ARMAsmBackendELF(T, TT, OSABI, isLittle);
   }
 }
 
 MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
                                           const MCRegisterInfo &MRI,
-                                          const Triple &TT, StringRef CPU) {
+                                          const TargetTuple &TT,
+                                          StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }
 
 MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const Triple &TT, StringRef CPU) {
+                                            const TargetTuple &TT,
+                                            StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, true);
 }
 
 MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
                                             const MCRegisterInfo &MRI,
-                                            const Triple &TT, StringRef CPU) {
+                                            const TargetTuple &TT,
+                                            StringRef CPU) {
   return createARMAsmBackend(T, MRI, TT, CPU, false);
 }
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
index 6b4abd5898e..ff007320f41 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
@@ -23,7 +23,7 @@ class ARMAsmBackend : public MCAsmBackend {
   bool isThumbMode;    // Currently emitting Thumb code.
   bool IsLittleEndian; // Big or little endian.
 public:
-  ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
+  ARMAsmBackend(const Target &T, const TargetTuple &TT, bool IsLittle)
       : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")),
         isThumbMode(TT.getArchName().startswith("thumb")),
         IsLittleEndian(IsLittle) {}
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
index a6206e3d958..b25f0a1bf9b 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
@@ -18,7 +18,7 @@ namespace {
 class ARMAsmBackendDarwin : public ARMAsmBackend {
 public:
   const MachO::CPUSubTypeARM Subtype;
-  ARMAsmBackendDarwin(const Target &T, const Triple &TT,
+  ARMAsmBackendDarwin(const Target &T, const TargetTuple &TT,
                       MachO::CPUSubTypeARM st)
       : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
     HasDataInCodeSupport = true;
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
index 68b12edd089..84d319146bb 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
@@ -15,7 +15,7 @@ namespace {
 class ARMAsmBackendELF : public ARMAsmBackend {
 public:
   uint8_t OSABI;
-  ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
+  ARMAsmBackendELF(const Target &T, const TargetTuple &TT, uint8_t OSABI,
                    bool IsLittle)
       : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
 
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
index 170f59a4c90..d5783b14c83 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
@@ -15,8 +15,8 @@ using namespace llvm;
 namespace {
 class ARMAsmBackendWinCOFF : public ARMAsmBackend {
 public:
-  ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
-      : ARMAsmBackend(T, TheTriple, true) {}
+  ARMAsmBackendWinCOFF(const Target &T, const TargetTuple &TT)
+      : ARMAsmBackend(T, TT, true) {}
   MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
     return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
   }
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
index a969d30041a..b858f1f82ee 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
@@ -1361,7 +1361,7 @@ MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S) {
 
 MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
                                                 const MCSubtargetInfo &STI) {
-  const Triple &TT = STI.getTargetTriple();
+  const TargetTuple &TT = STI.getTargetTuple();
   if (TT.isOSBinFormatELF())
     return new ARMTargetELFStreamer(S);
   return new ARMTargetStreamer(S);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
index 1ac08159bd3..90746468fe9 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
@@ -12,16 +12,16 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCAsmInfo.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 
 void ARMMCAsmInfoDarwin::anchor() { }
 
-ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
+ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const TargetTuple &TT) {
+  if ((TT.getArch() == TargetTuple::armeb) ||
+      (TT.getArch() == TargetTuple::thumbeb))
     IsLittleEndian = false;
 
   Data64bitsDirective = nullptr;
@@ -40,9 +40,9 @@ ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) {
 
 void ARMELFMCAsmInfo::anchor() { }
 
-ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
-  if ((TheTriple.getArch() == Triple::armeb) ||
-      (TheTriple.getArch() == Triple::thumbeb))
+ARMELFMCAsmInfo::ARMELFMCAsmInfo(const TargetTuple &TT) {
+  if ((TT.getArch() == TargetTuple::armeb) ||
+      (TT.getArch() == TargetTuple::thumbeb))
     IsLittleEndian = false;
 
   // ".comm align is in bytes but .align is pow-2."
@@ -56,9 +56,9 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) {
   SupportsDebugInformation = true;
 
   // Exceptions handling
-  switch (TheTriple.getOS()) {
-  case Triple::Bitrig:
-  case Triple::NetBSD:
+  switch (TT.getOS()) {
+  case TargetTuple::Bitrig:
+  case TargetTuple::NetBSD:
     ExceptionsType = ExceptionHandling::DwarfCFI;
     break;
   default:
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
index 5e548162bec..8e121a5b967 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h
@@ -19,20 +19,20 @@
 #include "llvm/MC/MCAsmInfoELF.h"
 
 namespace llvm {
-class Triple;
+class TargetTuple;
 
 class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin {
   virtual void anchor();
 
 public:
-  explicit ARMMCAsmInfoDarwin(const Triple &TheTriple);
+  explicit ARMMCAsmInfoDarwin(const TargetTuple &TT);
 };
 
 class ARMELFMCAsmInfo : public MCAsmInfoELF {
   void anchor() override;
 
 public:
-  explicit ARMELFMCAsmInfo(const Triple &TT);
+  explicit ARMELFMCAsmInfo(const TargetTuple &TT);
 
   void setUseIntegratedAssembler(bool Value) override;
 };
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index b88578309f0..ba2b6b1d03a 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -57,7 +57,7 @@ public:
     return isThumb(STI) && STI.getFeatureBits()[ARM::FeatureThumb2];
   }
   bool isTargetMachO(const MCSubtargetInfo &STI) const {
-    const Triple &TT = STI.getTargetTriple();
+    const TargetTuple &TT = STI.getTargetTuple();
     return TT.isOSBinFormatMachO();
   }
 
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 21c9fc1e58b..e2a26a7b487 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -15,7 +15,7 @@
 #include "ARMMCAsmInfo.h"
 #include "ARMMCTargetDesc.h"
 #include "InstPrinter/ARMInstPrinter.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/ADT/TargetTuple.h"
 #include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
@@ -130,16 +130,16 @@ static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
 #define GET_SUBTARGETINFO_MC_DESC
 #include "ARMGenSubtargetInfo.inc"
 
-std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
-  bool isThumb =
-      TT.getArch() == Triple::thumb || TT.getArch() == Triple::thumbeb;
+std::string ARM_MC::ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU) {
+  bool isThumb = TT.getArch() == TargetTuple::thumb ||
+                 TT.getArch() == TargetTuple::thumbeb;
 
   bool NoCPU = CPU == "generic" || CPU.empty();
   std::string ARMArchFeature;
   switch (TT.getSubArch()) {
   default:
     llvm_unreachable("invalid sub-architecture for ARM");
-  case Triple::ARMSubArch_v8:
+  case TargetTuple::ARMSubArch_v8:
     if (NoCPU)
       // v8a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -150,7 +150,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8";
     break;
-  case Triple::ARMSubArch_v8_1a:
+  case TargetTuple::ARMSubArch_v8_1a:
     if (NoCPU)
       // v8.1a: FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2,
       //      FeatureMP, FeatureHWDiv, FeatureHWDivARM, FeatureTrustZone,
@@ -161,7 +161,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features
       ARMArchFeature = "+v8.1a";
     break;
-  case Triple::ARMSubArch_v7m:
+  case TargetTuple::ARMSubArch_v7m:
     isThumb = true;
     if (NoCPU)
       // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
@@ -170,7 +170,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7em:
+  case TargetTuple::ARMSubArch_v7em:
     if (NoCPU)
       // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
       //       FeatureT2XtPk, FeatureMClass
@@ -179,7 +179,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7s:
+  case TargetTuple::ARMSubArch_v7s:
     if (NoCPU)
       // v7s: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureHasRAS
       //      Swift
@@ -188,7 +188,7 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v7:
+  case TargetTuple::ARMSubArch_v7:
     // v7 CPUs have lots of different feature sets. If no CPU is specified,
     // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
     // the "minimum" feature set and use CPU string to figure out the exact
@@ -200,13 +200,13 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
       // Use CPU to figure out the exact features.
       ARMArchFeature = "+v7";
     break;
-  case Triple::ARMSubArch_v6t2:
+  case TargetTuple::ARMSubArch_v6t2:
     ARMArchFeature = "+v6t2";
     break;
-  case Triple::ARMSubArch_v6k:
+  case TargetTuple::ARMSubArch_v6k:
     ARMArchFeature = "+v6k";
     break;
-  case Triple::ARMSubArch_v6m:
+  case TargetTuple::ARMSubArch_v6m:
     isThumb = true;
     if (NoCPU)
       // v6m: FeatureNoARM, FeatureMClass
@@ -214,19 +214,19 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
     else
       ARMArchFeature = "+v6";
     break;
-  case Triple::ARMSubArch_v6:
+  case TargetTuple::ARMSubArch_v6:
     ARMArchFeature = "+v6";
     break;
-  case Triple::ARMSubArch_v5te:
+  case TargetTuple::ARMSubArch_v5te:
     ARMArchFeature = "+v5te";
     break;
-  case Triple::ARMSubArch_v5:
+  case TargetTuple::ARMSubArch_v5:
     ARMArchFeature = "+v5t";
     break;
-  case Triple::ARMSubArch_v4t:
+  case TargetTuple::ARMSubArch_v4t:
     ARMArchFeature = "+v4t";
     break;
-  case Triple::NoSubArch:
+  case TargetTuple::NoSubArch:
     break;
   }
 
@@ -247,9 +247,9 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
   return ARMArchFeature;
 }
 
-MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const Triple &TT,
+MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(const TargetTuple &TT,
                                                   StringRef CPU, StringRef FS) {
-  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
+  std::string ArchFS = ARM_MC::ParseARMTargetTuple(TT, CPU);
   if (!FS.empty()) {
     if (!ArchFS.empty())
       ArchFS = (Twine(ArchFS) + "," + FS).str();
@@ -266,23 +266,23 @@ static MCInstrInfo *createARMMCInstrInfo() {
   return X;
 }
 
-static MCRegisterInfo *createARMMCRegisterInfo(const Triple &Triple) {
+static MCRegisterInfo *createARMMCRegisterInfo(const TargetTuple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
   return X;
 }
 
 static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
-                                     const Triple &TheTriple) {
+                                     const TargetTuple &TT) {
   MCAsmInfo *MAI;
-  if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO())
-    MAI = new ARMMCAsmInfoDarwin(TheTriple);
-  else if (TheTriple.isWindowsMSVCEnvironment())
+  if (TT.isOSDarwin() || TT.isOSBinFormatMachO())
+    MAI = new ARMMCAsmInfoDarwin(TT);
+  else if (TT.isWindowsMSVCEnvironment())
     MAI = new ARMCOFFMCAsmInfoMicrosoft();
-  else if (TheTriple.isOSWindows())
+  else if (TT.isOSWindows())
     MAI = new ARMCOFFMCAsmInfoGNU();
   else
-    MAI = new ARMELFMCAsmInfo(TheTriple);
+    MAI = new ARMELFMCAsmInfo(TT);
 
   unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true);
   MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
@@ -290,7 +290,8 @@ static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI,
   return MAI;
 }
 
-static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
+static MCCodeGenInfo *createARMMCCodeGenInfo(const TargetTuple &TT,
+                                             Reloc::Model RM,
                                              CodeModel::Model CM,
                                              CodeGenOpt::Level OL) {
   MCCodeGenInfo *X = new MCCodeGenInfo();
@@ -302,11 +303,11 @@ static MCCodeGenInfo *createARMMCCodeGenInfo(const Triple &TT, Reloc::Model RM,
   return X;
 }
 
-static MCStreamer *createELFStreamer(const Triple &T, MCContext &Ctx,
+static MCStreamer *createELFStreamer(const TargetTuple &TT, MCContext &Ctx,
                                      MCAsmBackend &MAB, raw_pwrite_stream &OS,
                                      MCCodeEmitter *Emitter, bool RelaxAll) {
   return createARMELFStreamer(Ctx, MAB, OS, Emitter, false,
-                              T.getArch() == Triple::thumb);
+                              TT.getArch() == TargetTuple::thumb);
 }
 
 static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
@@ -316,7 +317,7 @@ static MCStreamer *createARMMachOStreamer(MCContext &Ctx, MCAsmBackend &MAB,
   return createMachOStreamer(Ctx, MAB, OS, Emitter, false, DWARFMustBeAtTheEnd);
 }
 
-static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
+static MCInstPrinter *createARMMCInstPrinter(const TargetTuple &TT,
                                              unsigned SyntaxVariant,
                                              const MCAsmInfo &MAI,
                                              const MCInstrInfo &MII,
@@ -326,7 +327,7 @@ static MCInstPrinter *createARMMCInstPrinter(const Triple &T,
   return nullptr;
 }
 
-static MCRelocationInfo *createARMMCRelocationInfo(const Triple &TT,
+static MCRelocationInfo *createARMMCRelocationInfo(const TargetTuple &TT,
                                                    MCContext &Ctx) {
   if (TT.isOSBinFormatMachO())
     return createARMMachORelocationInfo(Ctx);
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
index fd30623d79a..0619f308909 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
@@ -32,7 +32,7 @@ class MCRelocationInfo;
 class MCTargetStreamer;
 class StringRef;
 class Target;
-class Triple;
+class TargetTuple;
 class raw_ostream;
 class raw_pwrite_stream;
 
@@ -40,11 +40,11 @@ extern Target TheARMLETarget, TheThumbLETarget;
 extern Target TheARMBETarget, TheThumbBETarget;
 
 namespace ARM_MC {
-std::string ParseARMTriple(const Triple &TT, StringRef CPU);
+std::string ParseARMTargetTuple(const TargetTuple &TT, StringRef CPU);
 
 /// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
 /// do not need to go through TargetRegistry.
-MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
+MCSubtargetInfo *createARMMCSubtargetInfo(const TargetTuple &TT, StringRef CPU,
                                           StringRef FS);
 }
 
@@ -65,22 +65,22 @@ MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
                                         MCContext &Ctx);
 
 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                  const Triple &TT, StringRef CPU,
+                                  const TargetTuple &TT, StringRef CPU,
                                   bool IsLittleEndian);
 
 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
-                                    const Triple &TT, StringRef CPU);
+                                    const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbLEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const Triple &TT, StringRef CPU);
+                                      const TargetTuple &TT, StringRef CPU);
 
 MCAsmBackend *createThumbBEAsmBackend(const Target &T,
                                       const MCRegisterInfo &MRI,
-                                      const Triple &TT, StringRef CPU);
+                                      const TargetTuple &TT, StringRef CPU);
 
 // Construct a PE/COFF machine code streamer which will generate a PE/COFF
 // object file.