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authorPeter Smith <peter.smith@linaro.org>2018-06-05 09:32:28 +0000
committerPeter Smith <peter.smith@linaro.org>2018-06-05 09:32:28 +0000
commit0aafe0cee5e52135f6dc85b06210a265c619955d (patch)
treeb3f2131b094b7257329333277a39e25e86f40bb9 /llvm/lib/Target/ARM
parent964b27fa21785706bf14768fffbbf9b799ad70e3 (diff)
downloadbcm5719-llvm-0aafe0cee5e52135f6dc85b06210a265c619955d.tar.gz
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[MC][ARM] Correct Thumb BL instruction range
The Thumb BL range is + or - either 16 Megabytes or 4 Megabytes depending on whether the CPU supports Thumb2 or the v8-m baseline ops. The existing check for BL range is incorrectly set at +- 32 Megabytes. This change corrects the higher range and uses the lower range if the featurebits don't have the necessary support for it. Differential Revision: https://reviews.llvm.org/D46305 llvm-svn: 333991
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp8
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
index 40278629a01..8df49903ffe 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
@@ -518,9 +518,11 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
return swapHalfWords(out, Endian == support::little);
}
case ARM::fixup_arm_thumb_bl: {
- // FIXME: We get both thumb1 and thumb2 in here, so we can only check for
- // the less strict thumb2 value.
- if (!isInt<26>(Value - 4)) {
+ if (!isInt<25>(Value - 4) ||
+ (!STI.getFeatureBits()[ARM::FeatureThumb2] &&
+ !STI.getFeatureBits()[ARM::HasV8MBaselineOps] &&
+ !STI.getFeatureBits()[ARM::HasV6MOps] &&
+ !isInt<23>(Value - 4))) {
Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
return 0;
}
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