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| author | Evan Cheng <evan.cheng@apple.com> | 2008-10-14 21:26:46 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-10-14 21:26:46 +0000 |
| commit | 07d53b1d33e0be27d5fba7f5bc749f3b7332418c (patch) | |
| tree | adc145207cc34b4f77d3599a7d8e3faefed55c28 /llvm/lib/Target/ARM | |
| parent | b7c01f5f4833db0ddfaa11e55f6e6276d499db08 (diff) | |
| download | bcm5719-llvm-07d53b1d33e0be27d5fba7f5bc749f3b7332418c.tar.gz bcm5719-llvm-07d53b1d33e0be27d5fba7f5bc749f3b7332418c.zip | |
Rename LoadX to LoadExt.
llvm-svn: 57526
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e70bb0bd96a..14c4526d1a0 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -131,10 +131,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) computeRegisterProperties(); // ARM does not have f32 extending load. - setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); // ARM does not have i1 sign extending load. - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); // ARM supports all 4 flavors of integer indexed load / store. for (unsigned im = (unsigned)ISD::PRE_INC; |
