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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:42:49 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:42:49 +0000 |
| commit | 16478c4ccfbc02056eb87f4290657fc5a6b5c4f6 (patch) | |
| tree | 02440693728c0d24a4dc7296393ee38aa01facf4 /llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | |
| parent | 3db2a858531dea160fef516cf29a50f9a08571f6 (diff) | |
| download | bcm5719-llvm-16478c4ccfbc02056eb87f4290657fc5a6b5c4f6.tar.gz bcm5719-llvm-16478c4ccfbc02056eb87f4290657fc5a6b5c4f6.zip | |
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
llvm-svn: 205871
Diffstat (limited to 'llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 57dcf3dede6..4aa64d3f50c 100644 --- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -3353,7 +3353,7 @@ static bool isGPR32Register(unsigned Reg) { case W7: case W8: case W9: case W10: case W11: case W12: case W13: case W14: case W15: case W16: case W17: case W18: case W19: case W20: case W21: case W22: case W23: case W24: case W25: case W26: case W27: - case W28: case W29: case W30: case WSP: + case W28: case W29: case W30: case WSP: case WZR: return true; } return false; @@ -3852,8 +3852,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // Insert WZR or XZR as destination operand. ARM64Operand *RegOp = static_cast<ARM64Operand *>(Operands[1]); unsigned ZeroReg; - if (RegOp->isReg() && - (isGPR32Register(RegOp->getReg()) || RegOp->getReg() == ARM64::WZR)) + if (RegOp->isReg() && isGPR32Register(RegOp->getReg())) ZeroReg = ARM64::WZR; else ZeroReg = ARM64::XZR; @@ -3962,7 +3961,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, uint64_t Op3Val = Op3CE->getValue(); uint64_t NewOp3Val = 0; uint64_t NewOp4Val = 0; - if (isGPR32Register(Op2->getReg()) || Op2->getReg() == ARM64::WZR) { + if (isGPR32Register(Op2->getReg())) { NewOp3Val = (32 - Op3Val) & 0x1f; NewOp4Val = 31 - Op3Val; } else { |
