diff options
| -rw-r--r-- | llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/MC/ARM64/aliases.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/ARM64/bitfield-encoding.s | 8 |
3 files changed, 15 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp index 57dcf3dede6..4aa64d3f50c 100644 --- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp +++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp @@ -3353,7 +3353,7 @@ static bool isGPR32Register(unsigned Reg) { case W7: case W8: case W9: case W10: case W11: case W12: case W13: case W14: case W15: case W16: case W17: case W18: case W19: case W20: case W21: case W22: case W23: case W24: case W25: case W26: case W27: - case W28: case W29: case W30: case WSP: + case W28: case W29: case W30: case WSP: case WZR: return true; } return false; @@ -3852,8 +3852,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, // Insert WZR or XZR as destination operand. ARM64Operand *RegOp = static_cast<ARM64Operand *>(Operands[1]); unsigned ZeroReg; - if (RegOp->isReg() && - (isGPR32Register(RegOp->getReg()) || RegOp->getReg() == ARM64::WZR)) + if (RegOp->isReg() && isGPR32Register(RegOp->getReg())) ZeroReg = ARM64::WZR; else ZeroReg = ARM64::XZR; @@ -3962,7 +3961,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, uint64_t Op3Val = Op3CE->getValue(); uint64_t NewOp3Val = 0; uint64_t NewOp4Val = 0; - if (isGPR32Register(Op2->getReg()) || Op2->getReg() == ARM64::WZR) { + if (isGPR32Register(Op2->getReg())) { NewOp3Val = (32 - Op3Val) & 0x1f; NewOp4Val = 31 - Op3Val; } else { diff --git a/llvm/test/MC/ARM64/aliases.s b/llvm/test/MC/ARM64/aliases.s index 0afaa057652..c47c9fd1ed3 100644 --- a/llvm/test/MC/ARM64/aliases.s +++ b/llvm/test/MC/ARM64/aliases.s @@ -139,9 +139,13 @@ foo: mov w0, #0xffffffff mov w0, #0xffffff00 + mov wzr, #0xffffffff + mov wzr, #0xffffff00 ; CHECK: movn w0, #0 ; CHECK: movn w0, #255 +; CHECK: movn wzr, #0 +; CHECK: movn wzr, #255 ;----------------------------------------------------------------------------- ; MVN aliases diff --git a/llvm/test/MC/ARM64/bitfield-encoding.s b/llvm/test/MC/ARM64/bitfield-encoding.s index cdbac0848a3..a40906f40bb 100644 --- a/llvm/test/MC/ARM64/bitfield-encoding.s +++ b/llvm/test/MC/ARM64/bitfield-encoding.s @@ -11,6 +11,10 @@ foo: sbfm x1, x2, #1, #15 ubfm w1, w2, #1, #15 ubfm x1, x2, #1, #15 + sbfiz wzr, w0, #31, #1 + sbfiz xzr, x0, #31, #1 + ubfiz wzr, w0, #31, #1 + ubfiz xzr, x0, #31, #1 ; CHECK: bfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x33] ; CHECK: bfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xb3] @@ -18,6 +22,10 @@ foo: ; CHECK: sbfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0x93] ; CHECK: ubfm w1, w2, #1, #15 ; encoding: [0x41,0x3c,0x01,0x53] ; CHECK: ubfm x1, x2, #1, #15 ; encoding: [0x41,0x3c,0x41,0xd3] +; CHECK: sbfm wzr, w0, #1, #0 ; encoding: [0x1f,0x00,0x01,0x13] +; CHECK: sbfm xzr, x0, #33, #0 ; encoding: [0x1f,0x00,0x61,0x93] +; CHECK: lsl wzr, w0, #31 ; encoding: [0x1f,0x00,0x01,0x53] +; CHECK: ubfm xzr, x0, #33, #0 ; encoding: [0x1f,0x00,0x61,0xd3] ;==---------------------------------------------------------------------------== ; 5.4.5 Extract (immediate) |
