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| author | James Molloy <james.molloy@arm.com> | 2014-05-07 12:33:41 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2014-05-07 12:33:41 +0000 |
| commit | 4049e4fd771c5cf66b8733507dd91be23dc327dd (patch) | |
| tree | ac094f93d3c88f1ddd4eea03f3227a2388475fea /llvm/lib/Target/ARM64/ARM64ISelLowering.cpp | |
| parent | 4cd0782bf26d0c938a8ec5e043c0b4a4205f46aa (diff) | |
| download | bcm5719-llvm-4049e4fd771c5cf66b8733507dd91be23dc327dd.tar.gz bcm5719-llvm-4049e4fd771c5cf66b8733507dd91be23dc327dd.zip | |
[ARM64-BE] Implement the lane-twiddling logic at AAPCS boundaries for big endian.
The AAPCS states that values passed in registers must have a value as though
they had been loaded with "LDR". LDR is equivalent to "LD1.64 vX.1D" - that is,
loading scalars to vector registers and loading 1-element vectors is equivalent.
The logic implemented here is to ensure that at all call boundaries and during
formal argument lowering all vectors are treated as their bitwidth-based floating
point scalar counterpart, which is always one of f64 or f128 (v2i32 -> f64,
v4i32 -> f128 etc). A BITCAST is inserted so that the appropriate REV will be
generated during code generation.
llvm-svn: 208198
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64ISelLowering.cpp')
0 files changed, 0 insertions, 0 deletions
