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authorJames Molloy <james.molloy@arm.com>2014-05-07 12:33:55 +0000
committerJames Molloy <james.molloy@arm.com>2014-05-07 12:33:55 +0000
commitd3c401a2d0096431b24d29a7f25b71d633230795 (patch)
tree9b6e81bebaec8e85d591539ce4e07a6a5956edf3 /llvm/lib/Target/ARM64/ARM64FastISel.cpp
parent36132057da7749fdef028e1d1910c8117108e63b (diff)
downloadbcm5719-llvm-d3c401a2d0096431b24d29a7f25b71d633230795.tar.gz
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[ARM64-BE] Fix fast-isel, and add appropriate RUN lines to appropriate tests.
llvm-svn: 208200
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64FastISel.cpp')
-rw-r--r--llvm/lib/Target/ARM64/ARM64FastISel.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64FastISel.cpp b/llvm/lib/Target/ARM64/ARM64FastISel.cpp
index 1af50739099..78cde1c22c9 100644
--- a/llvm/lib/Target/ARM64/ARM64FastISel.cpp
+++ b/llvm/lib/Target/ARM64/ARM64FastISel.cpp
@@ -1593,6 +1593,11 @@ bool ARM64FastISel::SelectRet(const Instruction *I) {
EVT RVEVT = TLI.getValueType(RV->getType());
if (!RVEVT.isSimple())
return false;
+
+ // Vectors (of > 1 lane) in big endian need tricky handling.
+ if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
+ return false;
+
MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128)
return false;
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