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| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-25 00:33:29 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-25 00:33:29 +0000 |
| commit | f3a1fce8ae411ea7135bc48495e09538d492929e (patch) | |
| tree | 04b6da3b544e2edbe87580c4d28fc0e898bdc455 /llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | |
| parent | bcf2ae6aa56af3668906e1aed9687a3228d55188 (diff) | |
| download | bcm5719-llvm-f3a1fce8ae411ea7135bc48495e09538d492929e.tar.gz bcm5719-llvm-f3a1fce8ae411ea7135bc48495e09538d492929e.zip | |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb2InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Thumb2InstrInfo.cpp | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index f1ac2219762..4d442c0d54d 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -38,9 +38,6 @@ unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const { case ARMII::ADDrr: return ARM::t2ADDrr; case ARMII::B: return ARM::t2B; case ARMII::Bcc: return ARM::t2Bcc; - case ARMII::BR_JTr: return ARM::t2BR_JTr; - case ARMII::BR_JTm: return ARM::t2BR_JTm; - case ARMII::BR_JTadd: return ARM::t2BR_JTadd; case ARMII::BX_RET: return ARM::tBX_RET; case ARMII::LDRrr: return ARM::t2LDRs; case ARMII::LDRri: return ARM::t2LDRi12; @@ -64,9 +61,7 @@ Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { switch (MBB.back().getOpcode()) { case ARM::t2LDM_RET: case ARM::t2B: // Uncond branch. - case ARM::t2BR_JTr: // Jumptable branch. - case ARM::t2BR_JTm: // Jumptable branch through mem. - case ARM::t2BR_JTadd: // Jumptable branch add to pc. + case ARM::t2BR_JT: // Jumptable branch. case ARM::tBR_JTr: // Jumptable branch (16-bit version). case ARM::tBX_RET: case ARM::tBX_RET_vararg: |
