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authorJim Grosbach <grosbach@apple.com>2011-08-11 20:04:56 +0000
committerJim Grosbach <grosbach@apple.com>2011-08-11 20:04:56 +0000
commit2a50260f2f68677c540193b7117db524b61c6126 (patch)
tree5bb5dc175e1d970918643afd24c593b723314c1b /llvm/lib/Target/ARM/Disassembler
parentd0767f37c10212dfba029b56e8586c53e7affe5b (diff)
downloadbcm5719-llvm-2a50260f2f68677c540193b7117db524b61c6126.tar.gz
bcm5719-llvm-2a50260f2f68677c540193b7117db524b61c6126.zip
ARM STRBT assembly parsing and encoding.
llvm-svn: 137337
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 85e48c7165e..d5994220a0c 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -939,8 +939,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::STR_POST_REG:
case ARM::STRTr:
case ARM::STRTi:
- case ARM::STRBTr:
- case ARM::STRBTi:
+ case ARM::STRBT_POST_REG:
+ case ARM::STRBT_POST_IMM:
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
break;
default:
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