Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact.

Patch by James Molloy.

llvm-svn: 137647

1 files changed, 15 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index e7b555a22fe..852c52af8be 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1094,6 +1094,21 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
   unsigned P = fieldFromInstruction32(Insn, 24, 1);
 
   bool writeback = (W == 1) | (P == 0);
+
+  // For {LD,ST}RD, Rt must be even, else undefined.
+  switch (Inst.getOpcode()) {
+    case ARM::STRD:
+    case ARM::STRD_PRE:
+    case ARM::STRD_POST:
+    case ARM::LDRD:
+    case ARM::LDRD_PRE:
+    case ARM::LDRD_POST:
+      if (Rt & 0x1) return false;
+      break;
+  default:
+    break;
+  }
+
   if (writeback) { // Writeback
     if (P)
       U |= ARMII::IndexModePre << 9;