Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;

instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757

1 files changed, 13 insertions, 5 deletions

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 884a056ef5d..27683e39751 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -1098,12 +1098,20 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
       OpIdx += 1;
     }
 
-    // Disassemble the 12-bit immediate offset, which is the second operand in
-    // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
-    // 
     unsigned Imm12 = slice(insn, 11, 0);
-    int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
-    MI.addOperand(MCOperand::CreateImm(Offset));
+    if (Opcode == ARM::LDRBi12 || Opcode == ARM::LDRi12 ||
+        Opcode == ARM::STRBi12 || Opcode == ARM::STRi12) {
+      // Disassemble the 12-bit immediate offset, which is the second operand in
+      // $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).    
+      int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
+      MI.addOperand(MCOperand::CreateImm(Offset));
+    } else {
+      // Disassemble the 12-bit immediate offset, which is the second operand in
+      // $am2offset => (ops GPR, i32imm).
+      unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
+                                          IndexMode);
+      MI.addOperand(MCOperand::CreateImm(Offset));
+    }
     OpIdx += 1;
   } else {
     // The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of