From 8ca13deecfc7cb08486c4a44cfe3d74b82fceab6 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Sat, 12 Nov 2011 00:31:53 +0000 Subject: Re-apply 144430, this time with the associated isel and disassmbler bits. Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437 --- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 ---- 1 file changed, 4 deletions(-) (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp') diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 840f50bdf55..0b9b5d0e6d2 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2267,10 +2267,6 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, // Second input register switch (Inst.getOpcode()) { - case ARM::VST1q8: - case ARM::VST1q16: - case ARM::VST1q32: - case ARM::VST1q64: case ARM::VST1d8T: case ARM::VST1d16T: case ARM::VST1d32T: -- cgit v1.2.3