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| author | Owen Anderson <resistor@mac.com> | 2011-08-09 23:05:39 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2011-08-09 23:05:39 +0000 |
| commit | 3d2e0e9db69da97b159c4788f0b1200bc901ebc4 (patch) | |
| tree | 45377074620d29f6106152a5930263b8edc3ce22 /llvm | |
| parent | ecc4ffc9414c90b205c54f6851b4a08aaec4f366 (diff) | |
| download | bcm5719-llvm-3d2e0e9db69da97b159c4788f0b1200bc901ebc4.tar.gz bcm5719-llvm-3d2e0e9db69da97b159c4788f0b1200bc901ebc4.zip | |
Tighten operand checking on CPS instructions.
llvm-svn: 137172
Diffstat (limited to 'llvm')
4 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index dc19f4657c5..34b3e62a2e2 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -1390,6 +1390,7 @@ class CPS<dag iops, string asm_ops> let Inst{4-0} = mode; } +let DecoderMethod = "DecodeCPSInstruction" in { let M = 1 in def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode), "$imod\t$iflags, $mode">; @@ -1398,6 +1399,7 @@ let mode = 0, M = 0 in let imod = 0, iflags = 0, M = 1 in def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">; +} // Preload signals the memory system of possible future data/instruction access. // These are for disassembly only. diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index d7b88560d71..a3fa138ba64 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -83,6 +83,8 @@ static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst, const void *Decoder); static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val, @@ -1139,6 +1141,9 @@ static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, unsigned iflags = fieldFromInstruction32(Insn, 6, 3); unsigned mode = fieldFromInstruction32(Insn, 0, 5); + // imod == '01' --> UNPREDICTABLE + if (imod == 1) return false; + if (M && mode && imod && iflags) { Inst.setOpcode(ARM::CPS3p); Inst.addOperand(MCOperand::CreateImm(imod)); diff --git a/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt index d3a75cb80c2..10748e9b126 100644 --- a/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ b/llvm/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} -# XFAIL: * # invalid imod value (0b01) 0xc0 0x67 0x4 0xf1 diff --git a/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index cc6062eae4f..5202217b6a7 100644 --- a/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/llvm/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} -# XFAIL: * # invalid (imod, M, iflags) combination 0x93 0x1c 0x02 0xf1 |
