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authorAnton Korobeynikov <asl@math.spbu.ru>2009-11-07 15:20:32 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2009-11-07 15:20:32 +0000
commit226467d6a688b0ddafd60c6b0afb34c006819f49 (patch)
tree3bfc3ed5a9f729af4643ee6c30445c4d10d206fa /llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
parenta381effe724b60a048846b7104a35f2d8c6e6dd5 (diff)
downloadbcm5719-llvm-226467d6a688b0ddafd60c6b0afb34c006819f49.tar.gz
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It turns out that the testcase in question uncovered subreg-handling bug.
Add assert in asmprinter to catch such cases and xfail the tests. PR is to be filled. llvm-svn: 86375
Diffstat (limited to 'llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp')
-rw-r--r--llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
index 8686961db45..c49fee3a550 100644
--- a/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
+++ b/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp
@@ -137,6 +137,7 @@ void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
+ assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
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