diff options
| -rw-r--r-- | llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll | 1 |
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index a3f52cdf19d..c130ced6247 100644 --- a/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -347,9 +347,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, &ARM::DPR_VFP2RegClass); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; } else { - if (unsigned SubReg = MO.getSubReg()) - Reg = TRI->getSubReg(Reg, SubReg); - + assert(!MO.getSubReg() && "Subregs should be eliminated!"); O << getRegisterName(Reg); } break; diff --git a/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp index 8686961db45..c49fee3a550 100644 --- a/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp +++ b/llvm/lib/Target/ARM/AsmPrinter/ARMMCInstLower.cpp @@ -137,6 +137,7 @@ void ARMMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; + assert(!MO.getSubReg() && "Subregs should be eliminated!"); MCOp = MCOperand::CreateReg(MO.getReg()); break; case MachineOperand::MO_Immediate: diff --git a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index 0a06991db24..fe177c3ea46 100644 --- a/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/llvm/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s +; XFAIL: * target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-eabi" |
