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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-10 19:18:01 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-10 19:18:01 +0000 |
| commit | c14871cc6704f9ea2951b0f542be1ed5e211dd7c (patch) | |
| tree | d5533b32f08fee06c61f24706e74207ccccdfbf9 /llvm/lib/Target/ARM/AsmParser | |
| parent | 166c8048930302d916848e08a251fae05718743d (diff) | |
| download | bcm5719-llvm-c14871cc6704f9ea2951b0f542be1ed5e211dd7c.tar.gz bcm5719-llvm-c14871cc6704f9ea2951b0f542be1ed5e211dd7c.zip | |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
llvm-svn: 144301
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser')
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 37 |
1 files changed, 32 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index e68ecec301a..83e7aac2fbf 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -602,6 +602,14 @@ public: int64_t Value = CE->getValue(); return Value > 0 && Value < 33; } + bool isImm0_32() const { + if (Kind != k_Immediate) + return false; + const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value >= 0 && Value < 33; + } bool isImm0_65535() const { if (Kind != k_Immediate) return false; @@ -1217,6 +1225,11 @@ public: Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); } + void addImm0_32Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addImm0_65535Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); @@ -4542,14 +4555,28 @@ processInstruction(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { switch (Inst.getOpcode()) { // Handle the MOV complex aliases. - case ARM::ASRi: { - unsigned Amt = Inst.getOperand(2).getImm() + 1; - unsigned ShiftOp = ARM_AM::getSORegOpc(ARM_AM::asr, Amt); + case ARM::ASRi: + case ARM::LSRi: + case ARM::LSLi: + case ARM::RORi: { + ARM_AM::ShiftOpc ShiftTy; + unsigned Amt = Inst.getOperand(2).getImm(); + switch(Inst.getOpcode()) { + default: llvm_unreachable("unexpected opcode!"); + case ARM::ASRi: ShiftTy = ARM_AM::asr; break; + case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; + case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; + case ARM::RORi: ShiftTy = ARM_AM::ror; break; + } + // A shift by zero is a plain MOVr, not a MOVsi. + unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; + unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); MCInst TmpInst; - TmpInst.setOpcode(ARM::MOVsi); + TmpInst.setOpcode(Opc); TmpInst.addOperand(Inst.getOperand(0)); // Rd TmpInst.addOperand(Inst.getOperand(1)); // Rn - TmpInst.addOperand(MCOperand::CreateImm(ShiftOp)); // Shift value and ty + if (Opc == ARM::MOVsi) + TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty TmpInst.addOperand(Inst.getOperand(3)); // CondCode TmpInst.addOperand(Inst.getOperand(4)); TmpInst.addOperand(Inst.getOperand(5)); // cc_out |
