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| author | David Green <david.green@arm.com> | 2019-09-15 14:14:47 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-09-15 14:14:47 +0000 |
| commit | b325c057322ce14b5c561d8ac49508adab7649e5 (patch) | |
| tree | 61afc1dbb9a328634e30c70be0261320a0fdc36d /llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | |
| parent | b6a0faaa0c793aede7911be241b1895a9ebea41c (diff) | |
| download | bcm5719-llvm-b325c057322ce14b5c561d8ac49508adab7649e5.tar.gz bcm5719-llvm-b325c057322ce14b5c561d8ac49508adab7649e5.zip | |
[ARM] Masked loads and stores
Masked loads and store fit naturally with MVE, the instructions being easily
predicated. This adds lowering for the simple cases of masked loads and stores.
It does not yet deal with widening/narrowing or pre/post inc, and so is
currently behind an option.
The llvm masked load intrinsic will accept a "passthru" value, dictating the
values used for the zero masked lanes. In MVE the instructions write 0 to the
zero predicated lanes, so we need to match a passthru that isn't 0 (or undef)
with a select instruction to pull in the correct data after the load.
Differential Revision: https://reviews.llvm.org/D67186
llvm-svn: 371932
Diffstat (limited to 'llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index e74b2b1a2ba..e8ac760786f 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -36,6 +36,10 @@ using namespace llvm; #define DEBUG_TYPE "armtti" +static cl::opt<bool> EnableMaskedLoadStores( + "enable-arm-maskedldst", cl::Hidden, cl::init(false), + cl::desc("Enable the generation of masked loads and stores")); + static cl::opt<bool> DisableLowOverheadLoops( "disable-arm-loloops", cl::Hidden, cl::init(false), cl::desc("Disable the generation of low-overhead loops")); @@ -487,6 +491,22 @@ int ARMTTIImpl::getAddressComputationCost(Type *Ty, ScalarEvolution *SE, return BaseT::getAddressComputationCost(Ty, SE, Ptr); } +bool ARMTTIImpl::isLegalMaskedLoad(Type *DataTy) { + if (!EnableMaskedLoadStores || !ST->hasMVEIntegerOps()) + return false; + + if (DataTy->isVectorTy()) { + // We don't yet support narrowing or widening masked loads/stores. Expand + // them for the moment. + unsigned VecWidth = DataTy->getPrimitiveSizeInBits(); + if (VecWidth != 128) + return false; + } + + unsigned EltWidth = DataTy->getScalarSizeInBits(); + return EltWidth == 32 || EltWidth == 16 || EltWidth == 8; +} + int ARMTTIImpl::getMemcpyCost(const Instruction *I) { const MemCpyInst *MI = dyn_cast<MemCpyInst>(I); assert(MI && "MemcpyInst expected"); |

