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| author | Eugene Leviant <eleviant@accesssoftek.com> | 2017-10-20 14:29:17 +0000 |
|---|---|---|
| committer | Eugene Leviant <eleviant@accesssoftek.com> | 2017-10-20 14:29:17 +0000 |
| commit | 27b226fb654830e4e5511df9bac883af9d4816e8 (patch) | |
| tree | bd0786c7bb187198d77e85b039ea7c1e09d85b47 /llvm/lib/Target/ARM/ARMTargetMachine.cpp | |
| parent | 46b791921f3031d67e5708756fd459f80fb1177f (diff) | |
| download | bcm5719-llvm-27b226fb654830e4e5511df9bac883af9d4816e8.tar.gz bcm5719-llvm-27b226fb654830e4e5511df9bac883af9d4816e8.zip | |
[ARM] Use post-RA MI scheduler when +use-misched is set
Differential revision: https://reviews.llvm.org/D39100
llvm-svn: 316214
Diffstat (limited to 'llvm/lib/Target/ARM/ARMTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetMachine.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 9a191e42247..39b8df401aa 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -310,7 +310,14 @@ namespace { class ARMPassConfig : public TargetPassConfig { public: ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) { + if (TM.getOptLevel() != CodeGenOpt::None) { + ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(), + TM.getTargetFeatureString()); + if (STI.hasFeature(ARM::FeatureUseMISched)) + substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); + } + } ARMBaseTargetMachine &getARMTargetMachine() const { return getTM<ARMBaseTargetMachine>(); |
