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| author | Eugene Leviant <eleviant@accesssoftek.com> | 2017-10-20 14:29:17 +0000 |
|---|---|---|
| committer | Eugene Leviant <eleviant@accesssoftek.com> | 2017-10-20 14:29:17 +0000 |
| commit | 27b226fb654830e4e5511df9bac883af9d4816e8 (patch) | |
| tree | bd0786c7bb187198d77e85b039ea7c1e09d85b47 | |
| parent | 46b791921f3031d67e5708756fd459f80fb1177f (diff) | |
| download | bcm5719-llvm-27b226fb654830e4e5511df9bac883af9d4816e8.tar.gz bcm5719-llvm-27b226fb654830e4e5511df9bac883af9d4816e8.zip | |
[ARM] Use post-RA MI scheduler when +use-misched is set
Differential revision: https://reviews.llvm.org/D39100
llvm-svn: 316214
| -rw-r--r-- | llvm/lib/Target/ARM/ARMTargetMachine.cpp | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll | 3 |
2 files changed, 11 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 9a191e42247..39b8df401aa 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -310,7 +310,14 @@ namespace { class ARMPassConfig : public TargetPassConfig { public: ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) { + if (TM.getOptLevel() != CodeGenOpt::None) { + ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(), + TM.getTargetFeatureString()); + if (STI.hasFeature(ARM::FeatureUseMISched)) + substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); + } + } ARMBaseTargetMachine &getARMTargetMachine() const { return getTM<ARMBaseTargetMachine>(); diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll index 960ee87532b..2ced60fbf0d 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-alu.ll @@ -1,5 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED ; Check the latency for ALU shifted operand variants. ; @@ -60,6 +61,8 @@ ; CHECK: Ready ; CHECK-NEXT: A57UnitI +; Check that post RA MI scheduler is invoked with +use-misched +; POST-MISCHED: Before post-MI-sched target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv8r-arm-none-eabi" |
