diff options
| author | Diana Picus <diana.picus@linaro.org> | 2017-06-07 10:14:23 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-06-07 10:14:23 +0000 |
| commit | eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34 (patch) | |
| tree | 68f55c74ae761c53f8925d903bb56d85c60ed46c /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
| parent | 15b80a5b2354d7d32f8c1c3f4fe47cee83d56d79 (diff) | |
| download | bcm5719-llvm-eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34.tar.gz bcm5719-llvm-eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34.zip | |
[ARM] GlobalISel: Support G_OR
Same as the other binary operators:
- legalize to 32 bits
- map to GPRs
- select ORRrr thanks to TableGen'erated code
llvm-svn: 304890
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index ec8ac97ac3a..b4df168fc32 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -222,6 +222,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_SUB: case G_MUL: case G_AND: + case G_OR: case G_SDIV: case G_UDIV: case G_SEXT: |
