From eeb0aad8e4041fcc7baed47f0ca2777fcfddbc34 Mon Sep 17 00:00:00 2001 From: Diana Picus Date: Wed, 7 Jun 2017 10:14:23 +0000 Subject: [ARM] GlobalISel: Support G_OR Same as the other binary operators: - legalize to 32 bits - map to GPRs - select ORRrr thanks to TableGen'erated code llvm-svn: 304890 --- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp') diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index ec8ac97ac3a..b4df168fc32 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -222,6 +222,7 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_SUB: case G_MUL: case G_AND: + case G_OR: case G_SDIV: case G_UDIV: case G_SEXT: -- cgit v1.2.3