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| author | Diana Picus <diana.picus@linaro.org> | 2017-02-28 13:05:42 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-02-28 13:05:42 +0000 |
| commit | 5a7203a0afa0a525283d6c35478ff17a43f1487f (patch) | |
| tree | 6dabad0d435117122dff526b0c83b41022c6b654 /llvm/lib/Target/ARM/ARMInstructionSelector.cpp | |
| parent | 7a1d34bec08f6735cd43c9a486136bc0bab1d171 (diff) | |
| download | bcm5719-llvm-5a7203a0afa0a525283d6c35478ff17a43f1487f.tar.gz bcm5719-llvm-5a7203a0afa0a525283d6c35478ff17a43f1487f.zip | |
[ARM] GlobalISel: Select 32-bit G_CONSTANT
Put it into a register by means of a MOVi.
llvm-svn: 296471
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index dccd717eb99..d7e5220f924 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -313,6 +313,17 @@ bool ARMInstructionSelector::select(MachineInstr &I) const { I.setDesc(TII.get(ARM::ADDri)); MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp()); break; + case G_CONSTANT: { + unsigned Reg = I.getOperand(0).getReg(); + if (MRI.getType(Reg).getSizeInBits() != 32) + return false; + + assert(RBI.getRegBank(Reg, MRI, TRI)->getID() == ARM::GPRRegBankID && + "Expected constant to live in a GPR"); + I.setDesc(TII.get(ARM::MOVi)); + MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); + break; + } case G_STORE: case G_LOAD: { const auto &MemOp = **I.memoperands_begin(); |
