summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDiana Picus <diana.picus@linaro.org>2017-02-28 13:05:42 +0000
committerDiana Picus <diana.picus@linaro.org>2017-02-28 13:05:42 +0000
commit5a7203a0afa0a525283d6c35478ff17a43f1487f (patch)
tree6dabad0d435117122dff526b0c83b41022c6b654
parent7a1d34bec08f6735cd43c9a486136bc0bab1d171 (diff)
downloadbcm5719-llvm-5a7203a0afa0a525283d6c35478ff17a43f1487f.tar.gz
bcm5719-llvm-5a7203a0afa0a525283d6c35478ff17a43f1487f.zip
[ARM] GlobalISel: Select 32-bit G_CONSTANT
Put it into a register by means of a MOVi. llvm-svn: 296471
-rw-r--r--llvm/lib/Target/ARM/ARMInstructionSelector.cpp11
-rw-r--r--llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir19
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index dccd717eb99..d7e5220f924 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -313,6 +313,17 @@ bool ARMInstructionSelector::select(MachineInstr &I) const {
I.setDesc(TII.get(ARM::ADDri));
MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
break;
+ case G_CONSTANT: {
+ unsigned Reg = I.getOperand(0).getReg();
+ if (MRI.getType(Reg).getSizeInBits() != 32)
+ return false;
+
+ assert(RBI.getRegBank(Reg, MRI, TRI)->getID() == ARM::GPRRegBankID &&
+ "Expected constant to live in a GPR");
+ I.setDesc(TII.get(ARM::MOVi));
+ MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
+ break;
+ }
case G_STORE:
case G_LOAD: {
const auto &MemOp = **I.memoperands_begin();
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
index 847c10c2970..57fea9a5dba 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
@@ -19,6 +19,7 @@
define void @test_stores() #0 { ret void }
define void @test_gep() { ret void }
+ define void @test_constants() { ret void }
define void @test_soft_fp_double() #0 { ret void }
@@ -466,6 +467,24 @@ body: |
BX_RET 14, _, implicit %r0
...
---
+name: test_constants
+# CHECK-LABEL: name: test_constants
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+# CHECK: id: [[C:[0-9]+]], class: gpr
+body: |
+ bb.0:
+ %0(s32) = G_CONSTANT 42
+ ; CHECK: %[[C]] = MOVi 42, 14, _, _
+
+ %r0 = COPY %0(s32)
+ BX_RET 14, _, implicit %r0
+...
+---
name: test_soft_fp_double
# CHECK-LABEL: name: test_soft_fp_double
legalized: true
OpenPOWER on IntegriCloud