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authorRafael Espindola <rafael.espindola@gmail.com>2006-05-14 22:18:28 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-05-14 22:18:28 +0000
commitffdc24b8470ab8b0fe096162cf0b05656118cdbb (patch)
treebc570c2f4c7ca20d9015df155e2391ba84c22642 /llvm/lib/Target/ARM/ARMInstrInfo.cpp
parentb37e4105c2ca7fa58124268bea597cd4450752a6 (diff)
downloadbcm5719-llvm-ffdc24b8470ab8b0fe096162cf0b05656118cdbb.tar.gz
bcm5719-llvm-ffdc24b8470ab8b0fe096162cf0b05656118cdbb.zip
added a skeleton of the ARM backend
llvm-svn: 28301
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.cpp58
1 files changed, 58 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
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+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
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+//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the "Instituto Nokia de Tecnologia" and
+// is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the ARM implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARMInstrInfo.h"
+#include "ARM.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "ARMGenInstrInfo.inc"
+using namespace llvm;
+
+ARMInstrInfo::ARMInstrInfo()
+ : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
+}
+
+/// Return true if the instruction is a register to register move and
+/// leave the source and dest operands in the passed parameters.
+///
+bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
+ unsigned &SrcReg, unsigned &DstReg) const {
+ // We look for 3 kinds of patterns here:
+ // or with G0 or 0
+ // add with G0 or 0
+ // fmovs or FpMOVD (pseudo double move).
+ assert(0 && "not implemented");
+ return false;
+}
+
+/// isLoadFromStackSlot - If the specified machine instruction is a direct
+/// load from a stack slot, return the virtual or physical register number of
+/// the destination along with the FrameIndex of the loaded stack slot. If
+/// not, return 0. This predicate must return 0 if the instruction has
+/// any side effects other than loading from the stack slot.
+unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
+ assert(0 && "not implemented");
+ return 0;
+}
+
+/// isStoreToStackSlot - If the specified machine instruction is a direct
+/// store to a stack slot, return the virtual or physical register number of
+/// the source reg along with the FrameIndex of the loaded stack slot. If
+/// not, return 0. This predicate must return 0 if the instruction has
+/// any side effects other than storing to the stack slot.
+unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI,
+ int &FrameIndex) const {
+ assert(0 && "not implemented");
+ return 0;
+}
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