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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-06-27 21:52:45 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-06-27 21:52:45 +0000 |
| commit | f6f5aff038741794ea4ef6c0e2ca8c817c8b3cff (patch) | |
| tree | 619da763f92b86f9884dd2dd9e6952340c839fa0 /llvm/lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | ca9c48852832bd4a7fc1e0c1c932cfc6205c1b27 (diff) | |
| download | bcm5719-llvm-f6f5aff038741794ea4ef6c0e2ca8c817c8b3cff.tar.gz bcm5719-llvm-f6f5aff038741794ea4ef6c0e2ca8c817c8b3cff.zip | |
handle the "mov reg1, reg2" case in isMoveInstr
llvm-svn: 28945
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index c98ea8b79d6..5abe8d688d6 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -27,7 +27,19 @@ ARMInstrInfo::ARMInstrInfo() /// bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const { - return false; + MachineOpCode oc = MI.getOpcode(); + switch (oc) { + default: + return false; + case ARM::movrr: + assert(MI.getNumOperands() == 2 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + "Invalid ARM MOV instruction"); + SrcReg = MI.getOperand(1).getReg();; + DstReg = MI.getOperand(0).getReg();; + return true; + } } /// isLoadFromStackSlot - If the specified machine instruction is a direct |
