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| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-05-11 09:28:27 +0000 |
| commit | ddc67a76559e699ead5aa5f82cecfdebec75a8be (patch) | |
| tree | 2c0e00d96041c6acc95cb2993be718bb71f24cde /llvm/lib/Target/ARM/ARMInstrFormats.td | |
| parent | 5a719f9b9a4142f0d97894f37f084555146bb3d2 (diff) | |
| download | bcm5719-llvm-ddc67a76559e699ead5aa5f82cecfdebec75a8be.tar.gz bcm5719-llvm-ddc67a76559e699ead5aa5f82cecfdebec75a8be.zip | |
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
llvm-svn: 156609
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrFormats.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrFormats.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index 3af0d3fc327..c8966fb97a4 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -827,6 +827,8 @@ class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin, let Inst{7-4} = 0b0111; let Inst{9-8} = 0b00; let Inst{27-20} = opcod; + + let Unpredictable{9-8} = 0b11; } // Misc Arithmetic instructions. |
