From ddc67a76559e699ead5aa5f82cecfdebec75a8be Mon Sep 17 00:00:00 2001 From: Silviu Baranga Date: Fri, 11 May 2012 09:28:27 +0000 Subject: Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609 --- llvm/lib/Target/ARM/ARMInstrFormats.td | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target/ARM/ARMInstrFormats.td') diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index 3af0d3fc327..c8966fb97a4 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -827,6 +827,8 @@ class AExtI opcod, dag oops, dag iops, InstrItinClass itin, let Inst{7-4} = 0b0111; let Inst{9-8} = 0b00; let Inst{27-20} = opcod; + + let Unpredictable{9-8} = 0b11; } // Misc Arithmetic instructions. -- cgit v1.2.3