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| author | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
|---|---|---|
| committer | Duncan Sands <baldrick@free.fr> | 2011-09-06 19:07:46 +0000 |
| commit | f2641e1bc11b28db5722f7f6adec2ac416dd0f6c (patch) | |
| tree | d04aab6b335e35380abf9d67702cdd2448d23da5 /llvm/lib/Target/ARM/ARMISelLowering.h | |
| parent | cf9b1f6524436866cf5f8639193ebe89d92ae6b0 (diff) | |
| download | bcm5719-llvm-f2641e1bc11b28db5722f7f6adec2ac416dd0f6c.tar.gz bcm5719-llvm-f2641e1bc11b28db5722f7f6adec2ac416dd0f6c.zip | |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
llvm-svn: 139159
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 5bf85d482bd..b06e6594afe 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -255,6 +255,9 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; + /// getSetCCResultType - Return the value type to use for ISD::SETCC. + virtual EVT getSetCCResultType(EVT VT) const; + virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; |
