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| author | Tim Northover <tnorthover@apple.com> | 2013-08-28 14:39:19 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-08-28 14:39:19 +0000 |
| commit | f5769880d982dfbb416d1b5014108f259545c27e (patch) | |
| tree | 7be58998ce1c45c0a21a5a83c7289b5be72dd36d /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 179e2c0b1479c0b517a5157215c062e075144a41 (diff) | |
| download | bcm5719-llvm-f5769880d982dfbb416d1b5014108f259545c27e.tar.gz bcm5719-llvm-f5769880d982dfbb416d1b5014108f259545c27e.zip | |
ARM: Use "dmb sy" for barriers on M-class CPUs
The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.
llvm-svn: 189483
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 74353c1788a..063f1d46c7d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2600,7 +2600,10 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1)); AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); unsigned Domain = ARM_MB::ISH; - if (Subtarget->isSwift() && Ord == Release) { + if (Subtarget->isMClass()) { + // Only a full system barrier exists in the M-class architectures. + Domain = ARM_MB::SY; + } else if (Subtarget->isSwift() && Ord == Release) { // Swift happens to implement ISHST barriers in a way that's compatible with // Release semantics but weaker than ISH so we'd be fools not to use // it. Beware: other processors probably don't! |
