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| author | James Molloy <james.molloy@arm.com> | 2015-08-11 12:06:22 +0000 |
|---|---|---|
| committer | James Molloy <james.molloy@arm.com> | 2015-08-11 12:06:22 +0000 |
| commit | ea3a687a334c801ffeb7062730dfa87d1570b270 (patch) | |
| tree | 20810ee4e1f9efa9300cd3b11e3da69757c4dd77 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | db8ee4b5a9ebd94255198ab7348f51327f5c1230 (diff) | |
| download | bcm5719-llvm-ea3a687a334c801ffeb7062730dfa87d1570b270.tar.gz bcm5719-llvm-ea3a687a334c801ffeb7062730dfa87d1570b270.zip | |
[ARM] Replace ARMISD::VMINNM/VMAXNM with ISD::FMINNUM/FMAXNUM
NFCI. This replaces another custom ISDNode with a generic equivalent.
llvm-svn: 244591
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index c81b1e8815e..93e7a501e79 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -932,6 +932,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FTRUNC, MVT::f32, Legal); setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); setOperationAction(ISD::FRINT, MVT::f32, Legal); + setOperationAction(ISD::FMINNUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); if (!Subtarget->isFPOnlySP()) { setOperationAction(ISD::FFLOOR, MVT::f64, Legal); setOperationAction(ISD::FCEIL, MVT::f64, Legal); @@ -939,6 +941,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FTRUNC, MVT::f64, Legal); setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); setOperationAction(ISD::FRINT, MVT::f64, Legal); + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); } } @@ -1146,8 +1150,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::UMLAL: return "ARMISD::UMLAL"; case ARMISD::SMLAL: return "ARMISD::SMLAL"; case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; - case ARMISD::VMAXNM: return "ARMISD::VMAX"; - case ARMISD::VMINNM: return "ARMISD::VMIN"; case ARMISD::BFI: return "ARMISD::BFI"; case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; @@ -3661,26 +3663,26 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { case ISD::SETOGE: if (!DAG.isKnownNeverNaN(RHS)) break; - return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); + return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS); case ISD::SETUGT: case ISD::SETUGE: if (!DAG.isKnownNeverNaN(LHS)) break; case ISD::SETGT: case ISD::SETGE: - return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); + return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS); case ISD::SETOLT: case ISD::SETOLE: if (!DAG.isKnownNeverNaN(RHS)) break; - return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); + return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS); case ISD::SETULT: case ISD::SETULE: if (!DAG.isKnownNeverNaN(LHS)) break; case ISD::SETLT: case ISD::SETLE: - return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); + return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS); } } } |
