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| author | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:08:32 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2009-08-14 05:08:32 +0000 |
| commit | cce31f68318f807aac3ed2567d5ec5630699db08 (patch) | |
| tree | 3ff70aee74da19f21a19cbcece21fa925744f6bd /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 7a87d6694e2dd762b00f49f54b5820c6308ae6d2 (diff) | |
| download | bcm5719-llvm-cce31f68318f807aac3ed2567d5ec5630699db08.tar.gz bcm5719-llvm-cce31f68318f807aac3ed2567d5ec5630699db08.zip | |
During legalization, change Neon vdup_lane operations from shuffles to
target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
llvm-svn: 78993
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index a36fdbf2474..3c40192ea57 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -477,7 +477,7 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; - case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ"; + case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; case ARMISD::VLD2D: return "ARMISD::VLD2D"; case ARMISD::VLD3D: return "ARMISD::VLD3D"; case ARMISD::VLD4D: return "ARMISD::VLD4D"; @@ -2447,6 +2447,12 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { // of inconsistencies between legalization and selection. // FIXME: floating-point vectors should be canonicalized to integer vectors // of the same time so that they get CSEd properly. + if (SVN->isSplat()) { + int Lane = SVN->getSplatIndex(); + if (Lane != 0) + return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0), + DAG.getConstant(Lane, MVT::i32)); + } if (isVREVMask(SVN, 64)) return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0)); if (isVREVMask(SVN, 32)) |
