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author | Sam Parker <sam.parker@arm.com> | 2017-10-25 08:33:06 +0000 |
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committer | Sam Parker <sam.parker@arm.com> | 2017-10-25 08:33:06 +0000 |
commit | ccb209bb97a682268a8841e5505ab5d7cea1bd13 (patch) | |
tree | 12ba5583916397020d39e73d0c81621d30275688 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
parent | 6ec2b8ac775918c4cdb5e3920a8ac212dcc1097c (diff) | |
download | bcm5719-llvm-ccb209bb97a682268a8841e5505ab5d7cea1bd13.tar.gz bcm5719-llvm-ccb209bb97a682268a8841e5505ab5d7cea1bd13.zip |
[ARM] Swap cmp operands for automatic shifts
Swap the compare operands if the lhs is a shift and the rhs isn't,
as in arm and T2 the shift can be performed by the compare for its
second operand.
Differential Revision: https://reviews.llvm.org/D39004
llvm-svn: 316562
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 3f126024df3..7c8f6d99568 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -3857,6 +3857,12 @@ SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, break; } } + } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) && + (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) { + // In ARM and Thumb-2, the compare instructions can shift their second + // operand. + CC = ISD::getSetCCSwappedOperands(CC); + std::swap(LHS, RHS); } ARMCC::CondCodes CondCode = IntCCToARMCC(CC); |