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| author | Yi Kong <Yi.Kong@arm.com> | 2014-08-20 10:40:20 +0000 |
|---|---|---|
| committer | Yi Kong <Yi.Kong@arm.com> | 2014-08-20 10:40:20 +0000 |
| commit | c655f0c898ab43e8986ba1d47f66837c529e6c8a (patch) | |
| tree | c3106b4846aa6d1479fa2abd34bfd4ca14eac2e3 /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | 5d536073927953ac8aebcf04196755e2b75dc4ad (diff) | |
| download | bcm5719-llvm-c655f0c898ab43e8986ba1d47f66837c529e6c8a.tar.gz bcm5719-llvm-c655f0c898ab43e8986ba1d47f66837c529e6c8a.zip | |
ARM: Fix codegen for rbit intrinsic
LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.
The bug was originally introduced in r211057.
Differential Revision: http://reviews.llvm.org/D4980
llvm-svn: 216064
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 8c670e75dda..24992c7d6f2 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2642,9 +2642,9 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, switch (IntNo) { default: return SDValue(); // Don't custom lower most intrinsics. case Intrinsic::arm_rbit: { - assert(Op.getOperand(0).getValueType() == MVT::i32 && + assert(Op.getOperand(1).getValueType() == MVT::i32 && "RBIT intrinsic must have i32 type!"); - return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(0)); + return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1)); } case Intrinsic::arm_thread_pointer: { EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
