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authorDale Johannesen <dalej@apple.com>2007-03-20 21:54:54 +0000
committerDale Johannesen <dalej@apple.com>2007-03-20 21:54:54 +0000
commitbacf4acf65bb554da97ef624739c14210d768220 (patch)
tree38339cbbd52e6dd344d932a8daa57397644ff244 /llvm/lib/Target/ARM/ARMISelLowering.cpp
parentd05a1a2ade1ba9e865f8bc976262a161f4fd7edc (diff)
downloadbcm5719-llvm-bacf4acf65bb554da97ef624739c14210d768220.tar.gz
bcm5719-llvm-bacf4acf65bb554da97ef624739c14210d768220.zip
do not share old induction variables when this would result in invalid
instructions (that would have to be split later) llvm-svn: 35227
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelLowering.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index bd7fa5cf6c7..17a41c5aaaa 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1379,6 +1379,24 @@ bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
}
}
+/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
+/// and V works for isLegalAddressImmediate _and_ both can be applied
+/// simultaneously to the same instruction.
+bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S, int64_t V,
+ const Type* Ty) const {
+ if (V == 0)
+ return isLegalAddressScale(S, Ty);
+ return false;
+}
+
+/// isLegalAddressScaleAndImm - Return true if S works for IsLegalAddressScale
+/// and GV works for isLegalAddressImmediate _and_ both can be applied
+/// simultaneously to the same instruction.
+bool ARMTargetLowering::isLegalAddressScaleAndImm(int64_t S,
+ GlobalValue *GV) const {
+ return false;
+}
+
static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
bool isSEXTLoad, SDOperand &Base,
SDOperand &Offset, bool &isInc,
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