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| author | Craig Topper <craig.topper@intel.com> | 2017-09-12 03:50:44 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-09-12 03:50:44 +0000 |
| commit | afdc36ed74fc151917947e43b0da6dba0df65752 (patch) | |
| tree | 234c2685dc9c9dede8971d53ea96095f311ebd7d /llvm/lib/Target/ARM/ARMISelLowering.cpp | |
| parent | f162013e6e5eef49af8e2d2ba185a3e995d8ec72 (diff) | |
| download | bcm5719-llvm-afdc36ed74fc151917947e43b0da6dba0df65752.tar.gz bcm5719-llvm-afdc36ed74fc151917947e43b0da6dba0df65752.zip | |
[X86] Add an extra instruction to TruncAssertSext.ll to prevent the 'or' from being narrowed so that the movl is really required to avoid a miscompile.
If we allow the OR to be narrowed then the upper bits really are zero and we can't tell if the zeroing movl was removed on purpose.
While here regenerate the test with update_llc_test_checks.py
llvm-svn: 312995
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelLowering.cpp')
0 files changed, 0 insertions, 0 deletions
